YARI is an open source FPGA microprocessor implementation, created as a vehicle to investigate implementation ideas. To avoid the burden of having to provide a complete tool-chain the instruction set is designed to be mostly compatible with the MIPS® architecture, a seminal, thoroughly documented, and, for our purpose, sufficiently simple RISC architecture.

The primary focus of YARI is high performance through low CPI and cycle time. In a Cyclone it can reach an maximum frequency of 90 MHz and a cycles-pr-instruction (CPI) of 1.18 on the CACAO benchmark. The resource consumption range from 2,000 LUT (MCU configuration) to 5,000 LUT (full SoC).

Unusual amount most open source soft cores, the implementation of YARI places great emphasis on avoiding pipeline stalls due to memory operations. To this end, YARI is equipped with 4-way associative instruction and data caches as well a a store buffer.

The distribution package includes a complete SoC, simulator, GDB stub, scripts, and various examples.



  1. Migrated to Github! The url is


  1. Migrated to SourceForge! The url is

  2. Major restructuring of the tree - targets are now top-level and everything common is below shared. Currently only DE2-70 and BeMicro have been updated to the new scheme, but the rest will follow eventually.

  3. Support for BeMicro SDK is likely in near future ...

  4. Added a Sigma-Delta pulse density modulator to soclib


  1. Ported to the inexpensive BeMicro platform


  1. Added a ready-to-run demo/puzzlebobble branch for the DE2-70 platform


  1. First Xilinx port working, the Virtex 4 based ML401


  1. Web site overhaul


  1. Target DE2-70 boots out of FlashROM


  1. SDL ported to YARI

  2. Add a 1024x768x8 graphic video interface for DE2-70 (above photo shows YARI executing my Puzzle Bobble game)

For more news, see the git repository